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STM32F101x6 STM32F101x8 STM32F101xB
Access line, advanced ARM-based 32-bit MCU with Flash memory, six 16-bit timers, ADC and seven communication interfaces
Features
Core: ARM 32-bit CortexTM-M3 CPU - 36 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access - Single-cycle multiplication and hardware division Memories - 32 to 128 Kbytes of Flash memory - 6 to 16 Kbytes of SRAM Clock, reset and supply management - 2.0 to 3.6 V application supply and I/Os - POR, PDR and programmable voltage detector (PVD) - 4-to-16 MHz crystal oscillator - Internal 8 MHz factory-trimmed RC - Internal 40 kHz RC - PLL for CPU clock - 32 kHz oscillator for RTC with calibration Low power - Sleep, Stop and Standby modes - VBAT supply for RTC and backup registers Debug mode - Serial wire debug (SWD) and JTAG interfaces DMA - 7-channel DMA controller - Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs 1 x 12-bit, 1 s A/D converter (up to 16 channels) - Conversion range: 0 to 3.6 V - Temperature sensor Up to 80 fast I/O ports - 26/37/51/80 I/Os, all mappable on 16 external interrupt vectors, all 5 V-tolerant except for analog inputs
VFQFPN36 6 x 6 mm
LQFP48 7 x 7 mm
LQFP64 10 x 10 mm
LQFP100 14 x 14 mm
Up to 6 timers - Up to three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter - 2 watchdog timers (Independent and Window) - SysTick timer: 24-bit downcounter Up to 7 communication interfaces - Up to 2 x I2C interfaces (SMBus/PMBus) - Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) - Up to 2 SPIs (18 Mbit/s) ECOPACK(R) packages Device summary
Root part number STM32F101C6, STM32F101R6, STM32F101T6 STM32F101C8, STM32F101R8 STM32F101V8, STM32F101T8 STM32F101RB, STM32F101VB, STM32F101CB
Table 1.
Reference STM32F101x6 STM32F101x8 STM32F101xB

March 2008
Rev 6
1/74
www.st.com 1
Contents
STM32F101xx
Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 4 5
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1 Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2 5.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 5.3.10 5.3.11 5.3.12 5.3.13 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 28 Embedded reset and power control block characteristics . . . . . . . . . . . 29 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 47 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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STM32F101xx 5.3.14 5.3.15 5.3.16 5.3.17
Contents TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.1 6.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
7.1 Future family enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
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List of tables
STM32F101xx
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Device features and peripheral counts (STM32F101xx access line) . . . . . . . . . . . . . . . . . . 8 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 29 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 32 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 33 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Typical current consumption in Sleep mode, code with data processing code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Typical current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 High-speed user external (HSE) clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Low-speed user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 SCL frequency (fPCLK1= 36 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
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STM32F101xx Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52.
List of tables
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 64 LQPF100 - 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . 65 LQFP64 - 64-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . 66 LQFP48 - 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . 67 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
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List of figures
STM32F101xx
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. STM32F101xx access line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 STM32F101xx access line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 STM32F101xx access line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 STM32F101xx access line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 STM32F101xx access line VFQPFN36 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 31 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 32 Current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V . . . 34 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 I2C bus AC waveforms and measurement circuit(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SPI timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 SPI timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 61 Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . . 62 VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Recommended footprint (dimensions in mm)(1)(2)(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 LQFP100, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 LQFP64 - 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 LQFP48 - 48-pin low-profile quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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STM32F101xx
Introduction
1
Introduction
This datasheet contains the description of the STM32F101xx access line family features, pinout, electrical characteristics, mechanical data and ordering information. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming reference manual. For information on the CortexTM-M3 core please refer to the CortexTM-M3 Technical Reference Manual.
2
Description
The STM32F101xx access line family incorporates the high-performance ARM CortexTM-M3 32-bit RISC core operating at a 36 MHz frequency, high-speed embedded memories (Flash memory up to 128Kbytes and SRAM up to 16 Kbytes), and an extensive range of enhanced peripherals and I/Os connected to two APB buses. All devices offer standard communication interfaces (two I2Cs, two SPIs, and up to three USARTs), one 12-bit ADC and three general purpose 16-bit timers. The STM32F101 family operates in the - to +85C temperature range, from a 2.0 to 3.6 V 40 power supply. A comprehensive set of power-saving mode allows to design low-power applications. The complete STM32F101xx access line family includes devices in 3 different package types: from 36 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the STM32F101xx access line microcontroller family suitable for a wide range of applications:

Application control and user interface Medical and handheld equipment PC peripherals, gaming and GPS platforms Industrial applications: PLC, inverters, printers, and scanners Alarm systems, Video intercom, and HVAC
Figure 1 shows the general block diagram of the device family.
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Description
STM32F101xx
2.1
Device overview
Table 2. Device features and peripheral counts (STM32F101xx access line) Peripheral
Flash - Kbytes SRAM - Kbytes Communication Timers General purpose SPI IC USART
2
STM32F101Tx STM32F101Cx 32 6 2 1 1 2 64 10 3 1 1 2 32 6 2 1 1 2 64 10 3 2 2 3 128 16 3 2 2 3
STM32F101Rx 32 6 2 1 1 2 64 10 3 2 2 3 128 16
STM32F101Vx 64 10 3 2 2 3 1 16 channels 80 128 16
12-bit synchronized ADC number of channels GPIOs CPU frequency Operating voltage Operating temperatures Packages
1 10 channels 26
1 10 channels 37
1 16 channels 51
36 MHz 2.0 to 3.6 V Ambient temperature: -40 to +85 C (see Table 7) Junction temperature: -40 to +105 C (see Table 7) VFQFPN36 LQFP48 LQFP64 LQFP100
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STM32F101xx
Description
2.2
Overview
ARM(R) CortexTM-M3 core with embedded Flash and SRAM
The ARM CortexTM-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM CortexTM-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The STM32F101xx access line family having an embedded ARM core, is therefore compatible with all ARM tools and software.
Embedded Flash memory
Up to 128 Kbytes of embedded Flash is available for storing programs and data.
Embedded SRAM
Up to 16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.
Nested vectored interrupt controller (NVIC)
The STM32F101xx access line embeds a nested vectored interrupt controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of CortexTM-M3) and 16 priority levels.

Closely coupled NVIC gives low latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Support for tail-chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt latency.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detectors lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect external line with pulse width lower than the Internal APB2 clock period. Up to 80 GPIOs are connected to the 16 external interrupt lines.
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Description
STM32F101xx
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected and is monitored for failure. During such a scenario, it is disabled and software interrupt management follows. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator). Several prescalers allow the configuration of the AHB frequency, the High Speed APB (APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 36 MHz. See Figure 2 for details on the clock tree.
Boot modes
At startup, boot pins are used to select one of five boot options:

Boot from User Flash Boot from System Memory Boot from SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1. For further details please refer to AN2606.
Power supply schemes

VDD = 2.0 to 3.6 V: External power supply for I/Os and the internal regulator. Provided externally through VDD pins. VSSA, VDDA = 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs and PLL. In VDD range (ADC is limited at 2.4 V). VDDA and VSSA must be connected to VDD and VSS, respectively. VBAT = 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.
For more details on how to connect power pins, refer to Figure 10: Power supply scheme.
Power supply supervisor
The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded Programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 9: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD.
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STM32F101xx
Description
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.

MR is used in the nominal regulation mode (Run) LPR is used in the Stop mode Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered-down, inducing zero consumption (but the contents of the registers and SRAM are lost)
This regulator is always enabled after RESET. It is disabled in Standby Mode, providing high impedance output.
Low-power modes
The STM32F101xx access line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:
Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
Stop mode Stop mode allows to achieve the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output or the RTC alarm.
Standby mode The Standby mode allows to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI and the HSE RC oscillators are also switched off. After entering Standby mode, SRAM and registers content are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode.
DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general purpose timers TIMx and ADC.
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Description
STM32F101xx
RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers (ten 16-bit registers) can be used to store data when VDD power is not present. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural crystal deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to reset the device when a problem occurs, or as a free running timer for application time out management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.
SysTick timer
This timer is dedicated for OS, but could also be used as a standard down counter. It features:

A 24-bit down counter Autoreload capability Maskable system interrupt generation when the counter reaches 0. Programmable clock source
General purpose timers (TIMx)
There are up to 3 synchronizable standard timers embedded in the STM32F101xx access line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture, output compare, PWM or one pulse mode output. This gives up to 12 input captures / output compares / PWMs on the largest packages. They can work together via the Timer Link feature for synchronization or event chaining. The counter can be frozen in debug mode. Any of the standard timers can be used to generate PWM outputs. Each of the timers has independent DMA request generations.
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STM32F101xx
Description
IC bus
Up to two IC bus interfaces can operate in multi-master and slave modes. They can support standard and fast modes. They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded. They can be served by DMA and they support SM Bus 2.0/PM Bus.
Universal synchronous/asynchronous receiver transmitter (USART)
The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816 compliant and have LIN Master/Slave capability. The USART interfaces can be served by the DMA controller.
Serial peripheral interface (SPI)
Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable from 8-bit to 16-bit. The hardware CRC generation/verification supports basic SD Card/MMC modes. Both SPIs can be served by the DMA controller.
GPIOs (general purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as Peripheral Alternate Function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.
ADC (analog to digital converter)
The 12-bit Analog to Digital Converter has up to 16 external channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.
Temperature sensor
The temperature sensor has to generate a linear voltage with any variation in temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.
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Description
STM32F101xx
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. Figure 1. STM32F101xx access line block diagram
TRACECLK TRACED[0:3] as AS
TPIU SW/JTAG Trace/trig SWD
Cortex M3 CPU
Fmax : 36 MHz NVIC NVIC Dbus
Ibus
Flash obl Inte rfac e
JNTRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as AF
pbus
Trace Cont rol ler
POWER VOLT. REG. 3.3V TO 1.8V @VDD
VDD = 2 to 3.6V
VSS
Flash 128 KB 64 bit
BusM atrix
Syst em
SRAM 16 KB
PCLK1 PCLK 2 HCLK FCLK RC 8 MHz RC 42 kHz @VDDA @VBAT PLL & CLOCK MANAGT
@VDD XTAL OSC 4-16 MHz OSC_IN OSC_OUT
GP DMA
7 channels AHB: Fmax =36 MHz
IWDG Stand by in terface
@VDDA SUPPLY SUPERVISION POR / PDR PVD Rst Int
VBAT OSC32_IN OSC32_OUT TAMPER-RTC
NRST VDDA VSSA
XTAL 32 kHz AHB2 APB2 AHB2 APB 1 RTC AWU Back up reg
80AF PA[ 15:0] PB[ 15:0] PC[15:0] PD[15:0] PE[15:0]
EXTI WAKEUP GPIOA
Backu p i nterf ace TIM2 TIM3 4 Chann els 4 Chann els 4 Channels RX,TX, CTS, RTS, CK, SmartCard as AF RX,TX, CTS, RTS, CK, SmartCard as AF MOSI,MISO,SCK,NSS as AF SCL,SDA,SMBA L as AF SCL,SDA as AF
GPIOB APB 1 : Fmax =24 / 36 MHz TIM4 USART2 USART3 SPI2 2x(8x16bit) I2C1 I2C2 GPIOC GPIOD GPIOE APB2 : Fmax = 36 MHz
MOSI,MISO, SCK,NSS as AF RX,TX, CTS, RTS, Smart Card as AF 16AF VREF+ VREF-
SPI1 USART1 @VDDA 12bit ADC1 IF
WWDG
Temp sen so r
ai14385B
1. AF = alternate function on I/O port pin. 2. TA = -40 C to +85 C (junction temperature up to 125 C).
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STM32F101xx Figure 2. Clock tree
8 MHz HSI RC
HSI
Description
/2
36 MHz max Clock Enable (3 bits)
HCLK to AHB bus, core, memory and DMA to Cortex System timer FCLK Cortex free running clock PCLK1 to APB1 peripherals Peripheral Clock
Enable (13 bits)
PLLSRC
PLLMUL ..., x16 x2, x3, x4 PLL
HSI PLLCLK HSE
SW
SYSCLK
/8
36 MHz /1, 2..512 max
AHB Prescaler
APB1 Prescaler /1, 2, 4, 8, 16
36 MHz max
CSS
to TIM2, 3 TIM2,3, 4 and 4 If (APB1 prescaler =1) x1 TIMXCLK else x2 Peripheral Clock
Enable (3 bits)
PLLXTPRE OSC_OUT OSC_IN 4-16 MHz HSE OSC /2
APB2 Prescaler /1, 2, 4, 8, 16
36 MHz max Peripheral Clock Enable (11 bits)
PCLK2 to APB2 peripherals
/128 OSC32_IN OSC32_OUT LSE OSC 32.768 kHz
LSE to RTC
ADC Prescaler /2, 4, 6, 8 RTCCLK
to ADC
ADCCLK
RTCSEL[1:0] LSI RC 40 kHz
LSI to Independent Watchdog (IWDG)
IWDGCLK
Legend:
Main Clock Output
/2
PLLCLK HSI HSE SYSCLK
MCO
HSE = high-speed external clock signal HSI = high-speed internal clock signal LSI = low-speed internal clock signal LSE = low-speed external clock signal
MCO
ai15104
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 36 MHz. 2. To have an ADC conversion time of 1 s, APB2 must be at 14 MHz or 28 MHz.
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Pin descriptions
STM32F101xx
3
Pin descriptions
Figure 3. STM32F101xx access line LQFP100 pinout
VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
LQFP100
VDD_2 VSS_2 NC PA 13 PA 12 PA 11 PA 10 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12
PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1
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26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
STM32F101xx Figure 4. STM32F101xx access line LQFP64 pinout
Pin descriptions
VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0 OSC_IN PD1 OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1
ai14387b
Figure 5.
STM32F101xx access line LQFP48 pinout
VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0-OSC_IN PD1-OSC_OUT NRST VSSA VDDA PA0-WKUP PA1 PA2
48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 34 3 33 4 32 5 31 6 LQFP48 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24
VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12
PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1
ai14378c
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Pin descriptions Figure 6. STM32F101xx access line VFQPFN36 pinout
BOOT0
STM32F101xx
VSS_3
PA15
36 VDD_3 OSC_IN/PD0 OSC_OUT/PD1 NRST VSSA VDDA PA0-WKUP PA1 PA2 1 2 3 4 5 6 7 8 9 10
35
34
33
32
31
30
29
28 27 26 25 24 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 VDD_1
QFN36
11
12
13
14
15
16
17
19 18
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
VSS_1
PA14
PB7
PB6
PB5
PB4
PB3
23 22 21 20
ai14654
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STM32F101xx Table 3.
Pins VFQFPN36 LQFP100 LQFP48 LQFP64 Pin name Type(1)
Pin descriptions
Pin definitions
I / O level(2) Alternate functions(3) Main function(3) (after reset)
Default
Remap
1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
2 3 4 5 6 7
PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPERRTC(4) PC14-OSC32_IN(4) PC15OSC32_OUT(4) VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP
I/O I/O I/O I/O I/O S I/O I/O I/O S S I O I/O I/O I/O I/O I/O S S S S I/O
FT FT FT FT FT
PE2 PE3 PE4 PE5 PE6 VBAT PC13(5) PC14(5) PC15(5) VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0
TRACECLK TRACED0 TRACED1 TRACED2 TRACED3
TAMPER-RTC OSC32_IN OSC32_OUT
ADC_IN10 ADC_IN11 ADC_IN12 ADC_IN13
WKUP/USART2_CTS(8)/ ADC_IN0/ TIM2_CH1_ETR(8) USART2_RTS(8)/ ADC_IN1/TIM2_CH2(8) USART2_TX(8)/ ADC_IN2/TIM2_CH3(8) USART2_RX(8)/ ADC_IN3/TIM2_CH4(8)
11 12 13 -
15 16 17 18
24 25 26 27
8 9 10 -
PA1 PA2 PA3 VSS_4
I/O I/O I/O S
PA1 PA2 PA3 VSS_4
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Pin descriptions Table 3.
Pins VFQFPN36 LQFP100 LQFP48 LQFP64 Pin name Type(1)
STM32F101xx
Pin definitions (continued)
I / O level(2) Alternate functions(3) Main function(3) (after reset)
Default
Remap
14 15 16 17 18 19 20 21 22 23 24 25
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
11 12 13 14
VDD_4 PA4 PA5 PA6 PA7 PC4 PC5
S I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O S S I/O FT FT FT FT FT FT FT FT FT FT FT FT FT
VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2/BOOT1 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 PB12 SPI2_NSS(6) (8)/ I2C2_SMBAl(6)/ USART3_CK(6) (8) SPI2_SCK(6)(8)/ USART3_CTS(6)(8) SPI2_MISO(6)(8)/ USART3_RTS(6)(8) I2C2_SCL(6)/ USART3_TX(6) (8) I2C2_SDA(6)/ USART3_RX(6) (8) TIM2_CH3 TIM2_CH4 SPI1_NSS/ADC_IN4 USART2_CK(8)/ SPI1_SCK/ADC_IN5 SPI1_MISO/ADC_IN6/ TIM3_CH1(8) SPI1_MOSI/ADC_IN7/ TIM3_CH2(8) ADC_IN14 ADC_IN15 ADC_IN8/TIM3_CH3(8) ADC_IN9/TIM3_CH4(8)
15 16 17 18 19 -
PB0 PB1 PB2/BOOT1 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 PB12
26 27
34 35
52 53
-
PB13 PB14
I/O I/O
FT FT
PB13 PB14
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STM32F101xx Table 3.
Pins VFQFPN36 LQFP100 LQFP48 LQFP64 Pin name Type(1)
Pin descriptions
Pin definitions (continued)
I / O level(2) Alternate functions(3) Main function(3) (after reset)
Default
Remap
28 -
36 37 38 39
54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
20 21 22 23 24
PB15 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PC6 PC7 PC8 PC9 PA8 PA9 PA10 PA11 PA12
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
FT FT FT FT FT FT FT FT FT FT FT FT FT FT FT FT FT FT FT
PB15 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PC6 PC7 PC8 PC9 PA8 PA9 PA10 PA11 PA12 JTMS-SWDIO
SPI2_MOSI(6) (8) USART3_TX USART3_RX USART3_CK USART3_CTS TIM4_CH1 / USART3_RTS TIM4_CH2 TIM4_CH3 TIM4_CH4 TIM3_CH1 TIM3_CH2 TIM3_CH3 TIM3_CH4 USART1_CK/MCO USART1_TX(8) USART1_RX(8) USART1_CTS USART1_RTS PA13
29 30 31 32 33 34 35 36 37 38 5 6
40 41 42 43 44 45 46 47 48 49 50 51 52 53 5 6 54
25 PA13/JTMS/SWDIO 26 27 VSS_2 VDD_2
Not connected S S I/O I/O I/O I/O I/O I/O I/O I/O I/O FT FT FT FT FT FT FT FT FT VSS_2 VDD_2 JTCK/SWCLK JTDI PC10 PC11 PC12 OSC_IN
(7)
28 PA14/JTCK/SWCLK 29 PA15/JTDI PC10 PC11 PC12 2 3 PD0 PD1 PD2 PD3
PA14 PA15 TIM2_CH1_ETR/ SPI1_NSS USART3_TX USART3_RX USART3_CK
OSC_OUT(7) PD2 PD3 TIM3_ETR USART2_CTS
-
-
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Pin descriptions Table 3.
Pins VFQFPN36 LQFP100 LQFP48 LQFP64 Pin name Type(1)
STM32F101xx
Pin definitions (continued)
I / O level(2) Alternate functions(3) Main function(3) (after reset)
Default
Remap
39 40 41 42 43 44 45 46 47 48
55 56 57 58 59 60 61 62 63 64
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
30 31 32 33 34 35 36 1
PD4 PD5 PD6 PD7 PB3/JTDO PB4/JNTRST PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_3
I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O S S
FT FT FT FT FT FT
PD4 PD5 PD6 PD7 JTDO JNTRST PB5 PB3/TRACESWO PB4 I2C1_SMBAl I2C1_SCL(8)/ TIM4_CH1(6) (8) I2C1_SDA(8)/ TIM4_CH2(6) (8)
USART2_RTS USART2_TX USART2_RX USART2_CK TIM2_CH2 / SPI1_SCK TIM3_CH1 / SPI1_MISO TIM3_CH2 / SPI1_MOSI USART1_TX USART1_RX
FT FT
PB6 PB7 BOOT0
FT FT FT FT
PB8 PB9 PE0 PE1 VSS_3 VDD_3
TIM4_CH3(6) (8) TIM4_CH4(6) (8) TIM4_ETR(6)
I2C1_SCL I2C1_SDA
1. I = input, O = output, S = supply, HiZ= high impedance. 2. FT= 5 V tolerant. 3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 2 on page 8. 4. PC13, PC14 and PC15 are supplied through the power switch, and so their use in output mode is limited: they can be used only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time. 5. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 6. Available only on devices with a Flash memory density equal or higher than 64 Kbytes. 7. The pins number 2 and 3 in the VFQFPN36 package, and 5 and 6 in the LQFP48 and LQFP64 packages are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 package, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode. 8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com.
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STM32F101xx
Memory mapping
4
Memory mapping
The memory map is shown in Figure 7. Figure 7. Memory map
0xFFFF FFFF 0xE010 0000 0x6000 0000 0x4002 3400 0xFFFF FFFF 0x4002 3000 0x4002 2400 0x4002 2000
APB memory space
reserved reserved reserved CRC reserved Flash interface reserved RCC reserved DMA reserved
4K 1K 3K 1K 3K 1K 3K 1K 1K 1K 1K 1K 1K 1K 1K 2K 1K 1K 1K 1K 1K 1K 1K 35K 1K 1K 1K 1K 1K 1K 1K 1K 2K 1K 1K 2K 1K 1K 1K 1K 1K 7K 1K 1K 1K
7
0xE010 0000 Cortex-M3 internal peripherals 0xE000 0000
0x4002 1400 0x4002 1000 0x4002 0400 0x4002 0000
6
0xC000 0000
0x4001 3C00 0x4001 3800 0x4001 3400 0x4001 3000 USART1 reserved SPI1 reserved reserved ADC1 reserved 0x4001 1C00
5
0xA000 0000
0x4001 2C00 0x4001 2800 0x4001 2400
4
0x8000 0000
0x1FFF FFFF 0x1FFF F80F
0x4001 1800
reserved
Port E Port D Port C Port B Port A EXTI AFIO reserved
0x4001 1400 0x4001 1000 0x4001 0C00 0x4001 0800
Option Bytes 0x1FFF F800
3
0x1FFF F000 0x6000 0000
System memory
0x4001 0400 0x4001 0000
0x4000 7400
2
0x4000 0000 Peripherals reserved
0x4000 7000 0x4000 6C00 0x4000 6800 0x4000 6400 0x4000 6000
PWR BKP reserved reserved reserved reserved I2C2 I2C1 reserved
1
0x2000 0000 SRAM 0x0801 FFFF
0x4000 5C00 0x4000 5800 0x4000 5400
0x4000 4C00
0
0x0800 0000 0x0000 0000
Flash memory
0x4000 4800 0x4000 4400
USART3 USART2 reserved
Aliased to Flash, system memory or SRAM depending on 0x0000 0000 BOOT pins
Reserved
0x4000 3C00 0x4000 3800 0x4000 3400 0x4000 3000 0x4000 2C00 0x4000 2800
SPI2 reserved IWDG WWDG RTC reserved
0x4000 0C00 0x4000 0800 0x4000 0400 0x4000 0000 TIM4 TIM3 TIM2
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Electrical characteristics
STM32F101xx
5
5.1
Electrical characteristics
Test conditions
Unless otherwise specified, all voltages are referred to VSS.
5.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.3 V (for the 2 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 8.
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 9.
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STM32F101xx
Electrical characteristics
Figure 8.
Pin loading conditions
Figure 9.
Pin input voltage
STM32F101 PIN C=50pF
VIN
STM32F101 PIN
ai14123
ai14124
5.1.6
Power supply scheme
Figure 10. Power supply scheme
VBAT
1.8-3.6V
Po wer swi tch
Backup circuitry (OSC32K,RTC, Wake-up logic Backup registers)
OUT
Level shifter
GP I/Os
IN
IO Logic Kernel logic (CPU, Digital & Memories)
VDD
VDD 1/2/3/4/5 VSS
Regulator
5 x 100 nF + 1 x 10 F
VDD VREF
1/2/3/4/5
VDDA VREF+ VREFVSSA
ai14125c
10 nF + 1 F
10 nF + 1 F
ADC
Analog: RCs, PLL, ...
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Electrical characteristics
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5.1.7
Current consumption measurement
Figure 11. Current consumption measurement scheme
IDD_VBAT VBAT
IDD VDD
VDDA
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Electrical characteristics
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 4: Voltage characteristics, Table 5: Current characteristics, and Table 6: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 4.
Symbol VDD -VSS VIN |VDDx| |VSSX - VSS|
Voltage characteristics
Ratings External main supply voltage (including VDDA and VDD)(1) Input voltage on five volt tolerant pin(2) Input voltage on any other pin(2) Variations between different power pins Variations between all the different ground pins Electrostatic discharge voltage (human body model) Min -0.3 VSS -0.3 VSS - 0.3 50 50 Max 4.0 +5.5 VDD+0.3 50 mV 50 V Unit
VESD(HBM)
see Section 5.3.11: Absolute maximum ratings (electrical sensitivity)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded (see Table 5: Current characteristics). This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VINTable 5.
Symbol IVDD IVSS IIO
Current characteristics
Ratings Total current into VDD power lines (source)(1) Total current out of VSS ground lines (sink)(1) Max. 150 150 25 -25 5 5 5 25 mA Unit
Output current sunk by any I/O and control pin Output current source by any I/Os and control pin Injected current on NRST pin IINJ(PIN) (2)(3) Injected current on High-speed external OSC_IN and Lowspeed external OSC_IN pins Injected current on any other pin(4) IINJ(PIN)(2) Total injected current (sum of all I/O and control pins)(4)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN27/74
Electrical characteristics Table 6. Thermal characteristics
Ratings Storage temperature range Maximum junction temperature Value
STM32F101xx
Symbol TSTG TJ
Unit C C
-65 to +150 150
5.3
5.3.1
Operating conditions
General operating conditions
Table 7.
Symbol fHCLK fPCLK1 fPCLK2 VDD VBAT
General operating conditions
Parameter Internal AHB clock frequency Internal APB1 clock frequency Internal APB2 clock frequency Standard operating voltage Backup operating voltage LQFP100 Conditions Min 0 0 0 2 1.8 Max 36 36 36 3.6 3.6 434 444 mW LQFP48 VFQFPN36 Maximum power dissipation -40 -40 -40 363 1110 85 105 105 C C C V V MHz Unit
PD
Power dissipation at TA = 85 C(1)
LQFP64
TA TJ
Ambient temperature Junction temperature range
Low power dissipation
(2)
1. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 68). 2. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 68).
5.3.2
Operating conditions at power-up / power-down
Subject to general operating conditions for TA. Table 8.
Symbol tVDD
Operating conditions at power-up / power-down
Parameter VDD rise time rate VDD fall time rate Conditions Min 0 20 Max Unit s/V

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Electrical characteristics
5.3.3
Embedded reset and power control block characteristics
The parameters given in Table 9 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7. Table 9.
Symbol
.
Embedded reset and power control block characteristics
Parameter Conditions PLS[2:0]=000 (rising edge) PLS[2:0]=000 (falling edge) PLS[2:0]=001 (rising edge) PLS[2:0]=001 (falling edge) PLS[2:0]=010 (rising edge) PLS[2:0]=010 (falling edge) PLS[2:0]=011 (rising edge) Min 2.1 2 2.19 2.09 2.28 2.18 2.38 2.28 2.47 2.37 2.57 2.47 2.66 2.56 2.76 2.66 Typ 2.18 2.08 2.28 2.18 2.38 2.28 2.48 2.38 2.58 2.48 2.68 2.58 2.78 2.68 2.88 2.78 100 Falling edge Rising edge 1.8(1) 1.84 1.88 1.92 40 1.5 2.5 3.5 1.96 2.0 Max 2.26 2.16 2.37 2.27 2.48 2.38 2.58 2.48 2.69 2.59 2.79 2.69 2.9 2.8 3 2.9 Unit V V V V V V V V V V V V V V V V mV V V mV ms
VPVD
Programmable voltage detector level selection
PLS[2:0]=011 (falling edge) PLS[2:0]=100 (rising edge) PLS[2:0]=100 (falling edge) PLS[2:0]=101 (rising edge) PLS[2:0]=101 (falling edge) PLS[2:0]=110 (rising edge) PLS[2:0]=110 (falling edge) PLS[2:0]=111 (rising edge) PLS[2:0]=111 (falling edge)
VPVDhyst(2) VPOR/PDR VPDRhyst tRSTTEMPO(2)
PVD hysteresis Power on/power down reset threshold PDR hysteresis Reset temporization
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value. 2. Guaranteed by design, not tested in production.
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Electrical characteristics
STM32F101xx
5.3.4
Embedded reference voltage
The parameters given in Table 10 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7. Table 10.
Symbol VREFINT TS_vrefint(1)
Embedded internal reference voltage
Parameter Internal reference voltage ADC sampling time when reading the internal reference voltage Conditions -40 C < TA < +85 C Min 1.16 Typ 1.20 5.1 Max 1.24 17.1 Unit V s
1. Shortest sampling time can be determined in the application by multiple iterations.
5.3.5
Supply current characteristics
The current consumption is measured as described in Figure 11: Current consumption measurement scheme.
Maximum current consumption
The MCU is placed under the following conditions:

All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except if it is explicitly mentioned The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 36 MHz) Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK
The parameters given in Table 11 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7. Table 11. Maximum current consumption in Run mode, code with data processing running from Flash
Max(1) Symbol Parameter Conditions fHCLK TA = 85 C 36 MHz External clock (2), all peripherals enabled IDD Supply current in Run mode External clock (2), all peripherals Disabled 24 MHz 16 MHz 8 MHz 36 MHz 24 MHz 16 MHz 8 MHz
1. Data based on characterization results, not tested in production. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz; external clock is 9 MHz for fHCLK = 36 MHz.
Unit 28.6 19.9 14.7 8.6 mA 19.8 13.9 10.7 6.8
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STM32F101xx Table 12.
Electrical characteristics Maximum current consumption in Run mode, code with data processing running from RAM
Max Parameter Conditions fHCLK TA = 85 C 36 MHz(2) External clock (1), all peripherals enabled 24 MHz
(2)
Symbol
Unit 24 17.5 12.5 7.5 16 11.5 8.5 5.5 mA
16 MHz(2) 8 MHz(2)
IDD
Supply current in Run mode External clock(1) all peripherals disabled(2)
36 MHz 24 MHz 16 MHz 8 MHz
1. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz; external clock is 9 MHz for fHCLK = 36 MHz. 2. Based on characterization, not tested in production.
Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled
25
20 Consumption (mA)
15
10
36MHz 16MHz 8MHz
5
0 -40 0 25 70 85 Temperature (C)
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Electrical characteristics
STM32F101xx
Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled
16 14 12 Consumption (mA) 10 8 6 4 2 0 -40 0 25 70 85 Temperature (C) 36MHz 16MHz 8MHz
Table 13.
Maximum current consumption in Sleep mode, code running from Flash or RAM
Max Parameter Conditions fHCLK TA = 85 C 36 MHz(2) External clock(1) all peripherals enabled 24 MHz(2)
(2)
Symbol
Unit 15.5 11.5 8.5 5.5 mA 5 4.5 4 3
16 MHz
IDD
Supply current in Sleep mode External clock(1), all peripherals disabled(2)
8 MHz(2) 36 MHz 24 MHz 16 MHz 8 MHz
1. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz; external clock is 9 MHz for fHCLK = 36 MHz. 2. Based on characterization, not tested in production.
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STM32F101xx Table 14.
Symbol
Electrical characteristics
Typical and maximum current consumptions in Stop and Standby modes
Typ(1) Parameter Conditions VDD/ VBAT = 2.4 V VDD/VBAT = 3.3 V Max Unit TA = 85 C
Supply current in Stop mode IDD
Regulator in Run mode, Low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Regulator in Low Power mode, Low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Low-speed internal RC oscillator and independent watchdog OFF, low-speed oscillator and RTC OFF Low-speed oscillator and RTC ON
23.5
24
200(2)
13.5
14
180(2) A
Supply current in Standby mode(3) IDD_VBAT Backup domain supply current
1.7
2
4(2)
1.1
1.4
1.9(4)
1. Typical values are measured at TA = 25 C, VDD = 3.3 V, unless otherwise specified. 2. Data based on characterization results, tested in production at VDDmax and fHCLK max. 3. To have the Standby consumption with RTC ON, add IDD_VBAT (Low-speed oscillator and RTC ON) to IDD Standby (when VDD is present the Backup Domain is powered by VDD supply). 4. Data based on characterization results, not rested in production.
Figure 14. Current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V
Stop regulator ON 140 120 Consumption (A) 100 80 60 40 20 0 -45 25 70 90 Temperature (C) 3.3 V 3.6 V
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Figure 15. Current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V
140 120 Consumption (A) 100 80 60 40 20 0 -40 0 25 Temperature (C) 70 85 3.3 V 3.6 V
Figure 16. Current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V
Standby mode 3 2.5 Consumption (A) 2 1.5 1 0.5 0 -45 25 70 90 Temperature (C) 3.3 V 3.6 V
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Electrical characteristics
Typical current consumption
The MCU is placed under the following conditions:

All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except if it is explicitly mentioned The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 36 MHz) Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4
The parameters given in Table 15 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7. Table 15. Typical current consumption in Run mode, code with data processing running from Flash
Typ(1) Symbol Parameter Conditions fHCLK All peripherals enabled(2) 19 12.9 9.3 5.5 3.3 2.2 1.6 1.3 1.08 18.3 12.2 8.5 4.9 2.7 1.6 1.02 0.73 0.5 Typ(1) All peripherals disabled 14.8 10.1 7.4 4.6 2.8 1.9 1.45 1.25 1.06 mA 36 MHz 24 MHz Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz
1. Typical values are measures at TA = 25 C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Unit
36 MHz 24 MHz 16 MHz 8 MHz External clock(3) 4 MHz 2 MHz 1 MHz 500 kHz IDD Supply current in Run mode 125 kHz
14.1 9.5 6.8 4 2.2 1.4 0.9 0.67 0.48
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Electrical characteristics Table 16.
STM32F101xx
Typical current consumption in Sleep mode, code with data processing code running from Flash or RAM
Typ(1) Typ(1) All peripherals disabled 3.1 2.3 1.8 1.2 1.1 1 0.98 0.96 0.95 mA 36 MHz 24 MHz Running on High Speed Internal RC (HSI), AHB prescaler used to reduce the frequency 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz 7 4.8 3.2 1.6 1 0.72 0.56 0.49 0.43 2.5 1.8 1.2 0.6 0.5 0.47 0.44 0.42 0.41 Unit Parameter Conditions fHCLK
Symbol
All peripherals enabled(2) 7.6 5.3 3.8 2.1 1.6 1.3 1.11 1.04 0.98
36 MHz 24 MHz 16 MHz 8 MHz External clock
(3)
4 MHz 2 MHz 1 MHz 500 kHz
IDD
Supply current in Sleep mode
125 kHz
1. Typical values are measures at TA = 25 C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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STM32F101xx Table 17.
Symbol
Electrical characteristics Typical current consumption in Standby mode
Parameter Conditions Low-speed internal RC oscillator and independent watchdog OFF IDD Supply current in Low-speed internal RC oscillator and Standby mode(2) independent watchdog ON Low-speed internal RC oscillator ON, independent watchdog OFF VDD 3.3 V 2.4 V 3.3 V 2.4 V 3.3 V 2.4 V 3.3 V Low-speed oscillator and RTC ON 2.4 V 1.1 Typ(1) 2 1.5 3.4 A 2.6 3.2 2.4 1.4 A Unit
IDD_VBAT
Backup domain supply current
1. Typical values are measures at TA = 25 C, VDD = 3.3 V. 2. To obtain Standby consumption with RTC ON, add IDD_VBAT (Low-speed oscillator, RTC ON) to IDD Standby.
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Electrical characteristics
STM32F101xx
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 18. The MCU is placed under the following conditions:

all I/O pins are in input mode with a static value at VDD or VSS (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption - - with all peripherals clocked off with only one peripheral clocked on
ambient operating temperature and VDD supply voltage conditions summarized in Table 4. Peripheral current consumption
Peripheral TIM2 TIM3 TIM4 SPI2 Typical consumption at 25 C(1) 0.6 0.6 0.6 0.08 0.21 0.21 0.18 0.18 mA GPIO A GPIO B GPIO C GPIO D 0.21 0.21 0.21 0.21 0.21 1.4 0.24 0.35 Unit
Table 18.
APB1 USART2 USART3 I2C1 I2C2
APB2 GPIO E ADC1 SPI1 USART1
1.
(2)
fHCLK = 36 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral.
2. Specific conditions for ADC: fHCLK = 28 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/2, ADON bit in the ADC_CR2 register is set to 1.
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STM32F101xx
Electrical characteristics
5.3.6
External clock source characteristics
High-speed user external clock
The characteristics given in Table 19 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 7. Table 19.
Symbol fHSE_ext VHSEH VHSEL tw(HSE) tw(HSE) tr(HSE) tf(HSE) IL
High-speed user external (HSE) clock characteristics
Parameter User external clock source frequency(1) OSC_IN input pin high level voltage OSC_IN input pin low level voltage OSC_IN high or low time(1) OSC_IN rise or fall time(1) VSS VIN VDD 0.7VDD VSS 16 ns 5 1 A Conditions Min Typ 8 Max 25 VDD V 0.3VDD Unit MHz
OSC_IN Input leakage current
1. Value based on design simulation and/or technology characteristics. It is not tested in production.
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Electrical characteristics
STM32F101xx
Low-speed user external clock
The characteristics given in Table 20 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 7. Table 20.
Symbol fLSE_ext VLSEH VLSEL tw(LSE) tw(LSE) tr(LSE) tf(LSE) IL
Low-speed user external clock characteristics
Parameter User external clock source frequency(1) OSC32_IN input pin high level voltage OSC32_IN input pin low level voltage OSC32_IN high or low time(1) OSC32_IN rise or fall time(1) VSS VIN VDD 0.7VDD VSS 450 ns 5 1 A Conditions Min Typ 32.768 Max 1000 VDD V 0.3VDD Unit kHz
OSC32_IN Input leakage current
1. Value based on design simulation and/or technology characteristics. It is not tested in production.
Figure 17. High-speed external clock source AC timing diagram
VHSEH 90% VHSEL 10% tr(HSE) THSE tf(HSE) tW(HSE) tW(HSE) t
EXTER NAL CLOCK SOURC E
fHSE_ext OSC _IN
IL STM32F101 ai14127
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STM32F101xx Figure 18. Low-speed external clock source AC timing diagram
Electrical characteristics
VLSEH 90% VLSEL 10% tr(LSE) TLSE tf(LSE) tW(LSE) tW(LSE) t
EXTER NAL CLOCK SOURC E
fLSE_ext
OSC32_IN
IL STM32F101 ai14140b
High-speed external clock
The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 21. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 21.
Symbol fOSC_IN RF CL1 CL2(2) i2 gm(4) tSU(HSE)
(5)
HSE 4-16 MHz oscillator characteristics(1)
Parameter Oscillator frequency Feedback resistor Recommended load capacitance versus R = 30 equivalent serial resistance of the crystal (RS)(3) S HSE driving current Oscillator transconductance Startup time VDD = 3.3 V VIN = VSS with 30 pF load Startup VDD is stabilized 25 2 Conditions Min 4 Typ 8 200 30 Max 16 Unit MHz k pF
1
mA mA/V ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included when sizing CL1 and CL2 (10 pF can be used as a rough estimate of the combined pin and board capacitance). 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. Based on characterization results, not tested in production. 5. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer
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Electrical characteristics Figure 19. Typical application with an 8 MHz crystal
STM32F101xx
RESONATOR WITH IN TEGRATED CAPAC ITORS CL1 OSC_IN 8 MH z resonator CL2 REXT(1) OSC_OU T RF Bias controlled gain STM32F101xx ai14128 fHSE
1. REXT value depends on the crystal characteristics. Typical value is in the range of 5 to 6RS.
Low-speed external clock
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 22. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 22.
Symbol RF CL1 CL2 I2 gm tSU(LSE)(2)
LSE oscillator characteristics (fLSE = 32.768 kHz)
Parameter Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(1) LSE driving current Oscillator transconductance Startup time VDD is stabilized RS = 30 K VDD = 3.3 V VIN = VSS 5 3 Conditions Min Typ 5 15 Max Unit M pF
1.4
A A/V s
1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768 kHz. Refer to crystal manufacturer for more details 2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer
Figure 20. Typical application with a 32.768 kHz crystal
RESONATOR WITH IN TEGRATED CAPAC ITORS CL1 OSC32_IN 32.768 KH z resonator CL2 RF OSC32_OU T Bias controlled gain STM32F101xx fLSE
ai14129
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Electrical characteristics
5.3.7
Internal clock source characteristics
The parameters given in Table 23 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7.
High-speed internal (HSI) RC oscillator
Table 23.
Symbol fHSI Frequency TA = -40 to 85 C ACCHSI Accuracy of HSI oscillator TA = -10 to 85 C TA = 0 to 70 C at TA = 25 C tsu(HSI) IDD(HSI) HSI oscillator startup time HSI oscillator power consumption 1 80
HSI oscillator characteristics(1)
Parameter Conditions Min Typ 8 1 1 1 1 3 2.5 2.2 2 2 100 Max Unit MHz % % % % s A
1. VDD = 3.3 V, TA = - to 85 C unless otherwise specified. 40
LSI low speed internal RC oscillator
Table 24.
Symbol fLSI tsu(LSI) IDD(LSI)
LSI oscillator characteristics (1)
Parameter Frequency LSI oscillator startup time LSI oscillator power consumption 0.65 Conditions Min(2) 30 Typ 40 Max 60 85 1.2 Unit kHz s A
1. VDD = 3 V, TA = - to 85 C unless otherwise specified. 40 2. Value based on device characterization, not tested in production.
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Electrical characteristics
STM32F101xx
Wakeup time from low power mode
The wakeup times given in Table 25 is measured on a wakeup phase with a 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode:

Stop or Standby mode: the clock source is the RC oscillator Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7. Table 25.
Symbol
Low-power mode wakeup timings
Parameter Conditions Wakeup on HSI RC clock HSI RC wakeup time = 2 s HSI RC wakeup time = 2 s, Regulator wakeup from LP mode time = 5 s HSI RC wakeup time = 2 s, Regulator wakeup from power down time = 38 s Typ 1.8 3.6 s 5.4 Unit s
tWUSLEEP(1) Wakeup from Sleep mode Wakeup from Stop mode (regulator in run mode) tWUSTOP(1) Wakeup from Stop mode (regulator in low-power mode)
tWUSTDBY(1) Wakeup from Standby mode
50
s
1. The wakeup times are measured from the wakeup event to the point at which the user application code reads the first instruction.
5.3.8
PLL characteristics
The parameters given in Table 26 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7. Table 26.
Symbol
PLL characteristics
Parameter PLL input clock Test conditions Value Min Typ 8.0 40 16 60 36 200 Max(1) Unit MHz % MHz s
fPLL_IN fPLL_OUT tLOCK
PLL input clock duty cycle PLL multiplier output clock PLL lock time
1. Data based on device characterization, not tested in production.
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STM32F101xx
Electrical characteristics
5.3.9
Memory characteristics
Flash memory
The characteristics are given at TA = - to 85 C unless otherwise specified. 40 Table 27.
Symbol tprog tERASE tME
Flash memory characteristics
Parameter 16-bit programming time Page (1kB) erase time Mass erase time Conditions TA = - to +85 C 40 TA = - to +85 C 40 TA = - to +85 C 40 Read mode fHCLK = 36MHz with 2 wait states, VDD = 3.3 V Min 40 20 20 Typ 52.5 Max(1) 70 40 40 20 Unit s ms ms mA
IDD
Supply current
Write / Erase modes fHCLK = 36 MHz, VDD = 3.3 V Power-down mode / Halt, VDD = 3.0 to 3.6 V
5
mA
50 2 3.6
A V
Vprog
Programming voltage
1. Values based on characterization and not tested in production.
Table 28.
Symbol NEND tRET
Flash memory endurance and data retention
Value Parameter Endurance Data retention Conditions TA = -40 C to 85 C TA = 85 C, 1 kcycle(2) kcycle(2) Min(1) 10 30 Years 20 Unit Typ Max kcycles
TA = 55 C, 10
1. Values based on characterization not tested in production. 2. Cycling performed over the whole temperature range.
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Electrical characteristics
STM32F101xx
5.3.10
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (Electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 1000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in Table 29. They are based on the EMS levels and classes defined in application note AN1709. Table 29.
Symbol VFESD
EMS characteristics
Parameter Voltage limits to be applied on any I/O pin to induce a functional disturbance Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance Conditions VDD = 3.3 V, TA = +25 C, fHCLK=48 MHz conforms to IEC 1000-4-2 VDD = 3.3 V, TA = +25 C, fHCLK = 48 MHz conforms to IEC 1000-4-4 Level/Class 2B
VEFTB
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and pre qualification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as:

Corrupted program counter Unexpected reset Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
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STM32F101xx
Electrical characteristics
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with SAE J 1752/3 standard which specifies the test board and the pin loading. Table 30. EMI characteristics
Monitored frequency band 0.1 MHz to 30 MHz SEMI Peak level VDD = 3.3 V, TA = 2 5C, LQFP100 package compliant with SAE J 1752/3 30 MHz to 130 MHz 130 MHz to 1GHz SAE EMI Level Max vs. [fHSE/fHCLK] 8/36 MHz 7 8 13 3.5 dBV
Symbol Parameter
Conditions
Unit
5.3.11
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 31.
Symbol VESD(HBM)
ESD absolute maximum ratings
Ratings Electrostatic discharge voltage (human body model) Conditions TA = +25 C conforming to JESD22-A114 TA = +25 C conforming to JESD22-C101 Class 2 Maximum value(1) 2000 V II 500 Unit
Electrostatic discharge VESD(CDM) voltage (charge device model)
1. Values based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on 10 parts to assess the latch-up performance:

A supply overvoltage is applied to each power supply pin A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78 IC latch-up standard.
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Electrical characteristics Table 32.
Symbol LU
STM32F101xx
Electrical sensitivities
Parameter Static latch-up class Conditions TA = +105 C conforming to JESD78A Class II level A
5.3.12
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 33 are derived from tests performed under the conditions summarized in Table 7. All I/Os are CMOS and TTL compliant. Table 33.
Symbol VIL
I/O static characteristics
Parameter Conditions Min -0.5 TTL ports 2 2 -0.5 CMOS ports 0.65 VDD 200 5% VDD(4) VSS VIN VDD Standard I/Os VIN = 5 V I/O FT 1 A 3 30 30 40 40 5 50 50 k k pF Typ Max 0.8 V VDD+0.5 5.5V 0.35 VDD VDD+0.5 mV mV Unit
Input low level voltage(1) Standard IO input high level voltage(1)
VIH
IO FT(2) input high level voltage(1) Input low level voltage(1) Input high level voltage(1) Standard IO Schmitt trigger voltage hysteresis(3)
VIL VIH
V
Vhys
IO FT Schmitt trigger voltage hysteresis(3)
Ilkg
Input leakage current
(4)
RPU RPD CIO
Weak pull-up equivalent resistor(5) Weak pull-down equivalent resistor(6) I/O pin capacitance
VIN = VSS VIN = VDD
1. Values based on characterization results, and not tested in production. 2. FT = Five-volt tolerant. 3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 4. With a minimum of 100 mV. 5. Leakage could be higher than max. if negative current is injected on adjacent pins. 6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimum (~10% order).
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STM32F101xx
Electrical characteristics
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink +20 mA (with a relaxed VOL). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2:
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 5). The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 5).
Output voltage levels
Unless otherwise specified, the parameters given in Table 34 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7. All I/Os are CMOS and TTL compliant. Table 34.
Symbol VOL(1) VOH(2) VOL(1) VOH(2) VOL(1) VOH (2) VOL(1) VOH(2)
Output voltage characteristics
Parameter Output Low level voltage for an I/O pin when 8 pins are sunk at the same time Output High level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Conditions TTL port, IIO = +8 mA, 2.7 V < VDD < 3.6 V CMOS port IIO = +8 mA 2.7 V < VDD < 3.6 V Min Max 0.4 V VDD-0.4 0.4 V 2.4 1.3 V VDD-1.3 0.4 V VDD-0.4 Unit
IIO = +20 mA(3) 2.7 V < VDD < 3.6 V
IIO = +6 mA(3) 2 V < VDD < 2.7 V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 5 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 5 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 3. Based on characterization data, not tested in production.
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Electrical characteristics
STM32F101xx
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 21 and Table 35, respectively. Unless otherwise specified, the parameters given in Table 35 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7. Table 35.
MODEx [1:0] bit value(1)
I/O AC characteristics(1)
Symbol Parameter Conditions CL = 50 pF, VDD = 2 V to 3.6 V Max 2 125(3) CL = 50 pF, VDD = 2 V to 3.6 V 125 CL= 50 pF, VDD = 2 V to 3.6 V
(3)
Unit MHz
fmax(IO)out Maximum frequency(2) 10 tf(IO)out tr(IO)out Output high to low level fall time Output low to high level rise time
ns
fmax(IO)out Maximum frequency(2) 01 tf(IO)out tr(IO)out Output high to low level fall time Output low to high level rise time
10 25(3)
MHz
CL= 50 pF, VDD = 2 V to 3.6 V 25(3) CL= 30 pF, VDD = 2.7 V to 3.6 V 50 30 20 5(3) 8(3) 12(3) 5(3) 8(3) 12(3) 10
ns
MHz MHz MHz
Fmax(IO)out Maximum
Frequency(2)
CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V CL = 30 pF, VDD = 2.7 V to 3.6 V
11
tf(IO)out
Output high to low level fall time
CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V CL = 30 pF, VDD = 2.7 V to 3.6 V
ns
tr(IO)out
Output low to high level rise time Pulse width of external signals detected by the EXTI controller
CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V
-
tEXTIpw
ns
1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 21. 3. Values based on design simulation and validated on silicon, not tested in production.
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STM32F101xx Figure 21. I/O AC characteristics definition
90% 50% 10% EXT ERNAL OUTPUT ON 50pF tr(I O)out T 10% 50% 90%
Electrical characteristics
tr(I O)out
Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF
ai14131
5.3.13
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 33). Unless otherwise specified, the parameters given in Table 36 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7. Table 36.
Symbol VIL(NRST) VIH(NRST) Vhys(NRST) RPU VF(NRST) VNF(NRST)
NRST pin characteristics
Parameter NRST Input low level voltage NRST Input high level voltage NRST Schmitt trigger voltage hysteresis Weak pull-up equivalent resistor(1) NRST Input filtered pulse(2) 300 VIN = VSS 30 Conditions Min -0.5 2 200 40 50 100 k ns ns Typ Max 0.8 V VDD+0.5 Unit
NRST Input not filtered pulse(2)
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). 2. Values guaranteed by design, not tested in production.
Figure 22. Recommended NRST pin protection
VDD NRST(2) RPU FILTER 0.1 F Internal Reset
External reset circuit(1)
STM32F10xxx
ai14132b
1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 36. Otherwise the reset will not be taken into account by the device.
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Electrical characteristics
STM32F101xx
5.3.14
TIM timer characteristics
The parameters given in Table 37 are guaranteed by fabrication. Refer to Section 5.3.12: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 37.
Symbol tres(TIM)
TIMx(1) characteristics
Parameter Timer resolution time fTIMxCLK = 36 MHz Timer external clock frequency on CH1 to CH4 Timer resolution 16-bit counter clock period when internal clock is selected 1 fTIMxCLK = 36 MHz 0.0278 27.8 0 fTIMxCLK = 36 MHz 0 fTIMxCLK/2 18 16 65536 1820 65536 x 65536 Conditions Min 1 Max Unit tTIMxCLK ns MHz MHz bit tTIMxCLK s tTIMxCLK s
fEXT ResTIM tCOUNTER
tMAX_COUNT Maximum possible count
fTIMxCLK = 36 MHz
119.2
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.
5.3.15
Communications interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Table 38 are derived from tests performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 7. The STM32F101xx access line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 38. Refer also to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL).
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STM32F101xx Table 38.
Symbol tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO) tw(STO:STA) Cb
Electrical characteristics I2C characteristics
Standard mode I2C(1) Fast mode I2C(1)(2) Parameter Min SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time Start condition hold time Repeated Start condition setup time Stop condition setup time Stop to Start condition time (bus free) Capacitive load for each bus line
2C
Unit Max Min 1.3 s 4.0 250 0
(3)
Max
4.7
0.6 100 0(4) 1000 300 20+0.1Cb 20+0.1Cb 0.6 s 0.6 0.6 1.3 400 400 s s pF 900(3) 300 300 ns
4.0 4.7 4.0 4.7
1. Values based on standard I
protocol requirement, not tested in production.
2. fPCLK1 must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 4 MHz to achieve the maximum fast mode I2C frequency. 3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.
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Electrical characteristics Figure 23. I2C bus AC waveforms and measurement circuit(1)
VDD 4 .7 k IC bus VDD 4 .7 k
STM32F101xx
100 100
STM32F101
SDA SCL
S TART REPEATED S TART tsu(STA) SDA tf(SDA) th(STA) SCL tw(SCKH) S TART
tr(SDA) tw(SCKL)
tsu(SDA) th(SDA) S TOP
tsu(STA:STO)
tr(SCK)
tf(SCK)
tsu(STO)
ai14127b
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Table 39.
SCL frequency (fPCLK1= 36 MHz, VDD = 3.3 V)(1)(2)(3)
fSCL (kHz) 400 300 200 100 50 20 I2C_CCR value RP = 4.7 k TBD TBD TBD TBD TBD TBD
1. TBD = to be determined. 2. RP = External pull-up resistance, fSCL = I2C speed, 3. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the tolerance on the achieved speed 2%. These variations depend on the accuracy of the external components used to design the application.
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Electrical characteristics
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 40 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 7. Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 40.
Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) tsu(NSS)(2) th(NSS)(2) tw(SCKH)(2) tw(SCKL)(2) tsu(MI) (2) tsu(SI)(2) th(MI) (2) th(SI)
(2)
SPI characteristics(1)
Parameter SPI clock frequency Slave mode SPI clock rise and fall time NSS setup time NSS hold time SCK high and low time Data input setup time Master mode Data input setup time Slave mode Data input hold time Master mode Data input hold time Slave mode Slave mode, fPCLK = 36 MHz, Data output access time presc = 4 Slave mode, fPCLK = 24 MHz SPI1 SPI2 Capacitive load: C = 30 pF Slave mode Slave mode Master mode, fPCLK = 36 MHz, presc = 4 SPI1 SPI2 4 tPCLK 18 50 1 5 1 1 5 3 0 0 10 25 3 25 4 55 4 tPCLK ns 60 0 18 8 Conditions Master mode Min 0 Max 18 MHz Unit
ta(SO)(2)(3) tdis(SO) tv(SO)
(2)(4)
Data output disable time Slave mode Data output valid time Data output valid time Slave mode (after enable edge) Master mode (after enable edge) Slave mode (after enable edge) Data output hold time Master mode (after enable edge)
(2)(1)
tv(MO)(2)(1) th(SO)(2) th(MO)(2)
1. Remapped SPI1 characteristics to be determined. 2. Values based on design simulation and/or characterization results, and not tested in production. 3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z
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Electrical characteristics Figure 24. SPI timing diagram - slave mode and CPHA=0
STM32F101xx
NSS input tSU(NSS) SCK Input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 tc(SCK) th(NSS)
tw(SCKH) tw(SCKL) tv(SO) MS B O UT tsu(SI) tr(SCK) tf(SCK) LSB OUT
ta(SO) MISO OUT P UT MOSI I NPUT
th(SO) BI T6 OUT
tdis(SO)
M SB IN th(SI)
B I T1 IN
LSB IN
ai14134
Figure 25. SPI timing diagram - slave mode and CPHA=1(1)
NSS input tSU(NSS) SCK Input CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) th(NSS)
tw(SCKH) tw(SCKL) tr(SCK) tf(SCK)
ta(SO) MISO OUT P UT tsu(SI) MOSI I NPUT M SB IN
tv(SO) MS B O UT th(SI)
th(SO) BI T6 OUT
tdis(SO) LSB OUT
B I T1 IN
LSB IN
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1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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STM32F101xx Figure 26. SPI timing diagram - master mode(1)
High NSS input tc(SCK) SCK Input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1
Electrical characteristics
SCK Input
CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INP UT MOSI OUTUT tw(SCKH) tw(SCKL) MS BIN th(MI) M SB OUT tv(MO) B I T1 OUT th(MO)
ai14136
tr(SCK) tf(SCK) BI T6 IN LSB IN
LSB OUT
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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Electrical characteristics
STM32F101xx
5.3.16
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 41 are derived from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 7.
Note: Table 41.
Symbol VDDA VREF+ IVREF fADC fS(2) fTRIG(2) VAIN RAIN(2) RADC(2) CADC(2) tCAL(2) tlat(2) tlatr(2) tS(2) tSTAB(2) tCONV(2)
It is recommended to perform a calibration after each power-up. ADC characteristics
Parameter ADC power supply Positive reference voltage Current on the VREF input pin ADC clock frequency Sampling rate External trigger frequency Conversion voltage range(3) External input impedance Sampling switch resistance Internal sample and hold capacitor 5.9 Calibration time Injection trigger conversion latency Regular trigger conversion latency Sampling time Power-up time Total conversion time (including sampling time) fADC = 14 MHz 83 0.214 fADC = 14 MHz 3
(4)
Conditions
Min 2.4 2.4
Typ
Max 3.6 VDDA
Unit V V A MHz MHz kHz 1/fADC V k k pF s 1/fADC s 1/fADC s 1/fADC s 1/fADC s s 1/fADC
160(1) 0.6 0.05 fADC = 14 MHz 0 (VSSA or VREFtied to ground)
220(1) 14 1 823 17 VREF+
See Equation 1 and Table 42 1 5
0.143 fADC = 14 MHz 0.107 fADC = 14 MHz 1.5 0 1 fADC = 14 MHz 0 2
(4)
17.1 239.5 1 18
14 to 252 (tS for sampling +12.5 for successive approximation)
1. Data based on characterization results, not tested in production. 2. Guaranteed by design, not tested in production. 3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package. Refer to Section 3: Pin descriptions for further details. 4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 41.
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STM32F101xx Equation 1: RAIN max formula:
S R AIN < --------------------------------------------------------------- - R ADC N+2 f ADC x C ADC x ln ( 2 )
Electrical characteristics
t
The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 42.
RAIN max for fADC = 14 MHz(1)
Ts (cycles) tS (s) 0.11 0.54 0.96 2.04 2.96 3.96 5.11 17.1 1.2 10 19 41 60 80 104 350 RAIN max (k)
1.5 7.5 13.5 28.5 41.5 55.5 71.5 239.5
1. Data guaranteed by design, not tested in production.
Table 43.
Symbol ET EO EG ED EL
ADC accuracy - limited test conditions(1)
Parameter Total unadjusted error(3) Offset error(3)
(3) (3)
Test conditions fPCLK2 = 56 MHz, , fADC = 14 MHz, RAIN < 10 k VDDA = 3 V to 3.6 V TA = 25 C Measurements made after ADC calibration VREF+ = VDDA
Typ 1.3 1 0.5 0.7 0.8
Max(2) 2 1.5 1.5 1 1.5
Unit
Gain error
LSB
Differential linearity error Integral linearity error(3)
1. ADC DC accuracy values are measured after internal calibration. 2. Data based on characterization, not tested in production. 3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not affect the ADC accuracy.
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Electrical characteristics Table 44.
Symbol ET EO EG ED EL
STM32F101xx
ADC accuracy(1) (2)
Parameter Total unadjusted error(4) Offset error(3)
(3)
Test conditions fPCLK2 = 56 MHz, , fADC = 14 MHz, RAIN < 10 k VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration
Typ 2 1.5 1.5 1 1.5
Max(3) 5 2.5 3 2 3
Unit
Gain error
LSB
Differential linearity error(3) Integral linearity error
(3)
1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be achieved in restricted VDD, frequency, VREF and temperature ranges. 3. Data based on characterization, not tested in production. 4. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not affect the ADC accuracy.
Figure 27. ADC accuracy characteristics
V V [1LSBIDEAL = REF+ (or DDA depending on package)] 4096 4096
EG 4095 4094 4093 (2) ET 7 6 5 4 3 2 1 0 1 VSSA 2 3 4 1 LSBIDEAL EO EL ED (3) (1) ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line
5
6
7
4093 4094 4095 4096 VDDA
ai14395b
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STM32F101xx Figure 28. Typical connection diagram using the ADC
VDD VT 0.6 V AINx VT 0.6 V
Electrical characteristics
STM32F101
RAIN(1)
RADC(1)
12-bit A/D conversion CADC(1)
VAIN
CAIN
IL1 A
ai14139b
1. Refer to Table 41 for the values of RAIN, RADC and CADC. 2. CPARASITIC must be added to CAIN. It represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (3 pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 29 or Figure 30, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 29. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32F101xx
V REF+
1 F // 10 nF
V DDA
1 F // 10 nF V SSA/V REF-
ai14380
1. VREF+ and VREF- inputs are available only on 100-pin packages.
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Electrical characteristics
STM32F101xx
Figure 30. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32F101xx
VREF+/VDDA
1 F // 10 nF
VREF-/VSSA
ai14380
1. VREF+ and VREF- inputs are available only on 100-pin packages.
5.3.17
Temperature sensor characteristics
Table 45.
Symbol
TS characteristics
Parameter VSENSE linearity with temperature 4.0 1.34 4 2.2 Conditions Min Typ Max Unit C mV/C V s s
TL(1)
1
4.3 1.43
2
4.6 1.52 10 17.1
Avg_Slope(1) Average slope V25(1) tSTART(2) TS_temp(3)(2) Voltage at 25C Startup time ADC sampling time when reading the temperature
1. Guaranteed by characterization, not tested in production. 2. Data guaranteed by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations.
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STM32F101xx
Package characteristics
6
6.1
Package characteristics
Package mechanical data
In order to meet environmental requirements, ST offers the STM32F101xx in ECOPACK(R) packages. These packages have a Lead-free second-level interconnect. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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Package characteristics
STM32F101xx
Figure 31. VFQFPN36 6 x 6 mm, 0.5 mm pitch, Figure 32. Recommended footprint package outline(1) (dimensions in mm)(1)(2)(3)
Seating plane C A2 A
36
ddd
C
4.30
A3 D e 28 27 36
A1 Pin # 1 ID R = 0.20
1
27
4.80
1
6.30
4.80
4.10
4.30
E2
b E
0.30 9
4.10
19 1.00
19 18 D2 10
9
0.75
10
18
0.50 4.30
L
ZR_ME
ai14870
1. Drawing is not to scale. 2. The back-side pad is not internally connected to the VSS or VDD power pads. 3. There is an exposed die pad on the underside of the VFQFPN package. It should be soldered to the PCB. All leads should also be soldered to the PCB.
Table 46.
Symbol
VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data
millimeters Min Typ 0.900 0.020 0.650 0.250 0.180 5.875 1.750 5.875 1.750 0.450 0.350 0.230 6.000 3.700 6.000 3.700 0.500 0.550 0.080 0.300 6.125 4.250 6.125 4.250 0.550 0.750 0.0071 0.2313 0.0689 0.2313 0.0689 0.0177 0.0138 Max 1.000 0.050 1.000 Min 0.0315 inches(1) Typ 0.0354 0.0008 0.0256 0.0098 0.0091 0.2362 0.1457 0.2362 0.1457 0.0197 0.0217 0.0031 0.0118 0.2411 0.1673 0.2411 0.1673 0.0217 0.0295 Max 0.0394 0.0020 0.0394
A A1 A2 A3 b D D2 E E2 e L ddd
0.800
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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STM32F101xx
Package characteristics Figure 34. Recommended footprint(1)(2)
Figure 33. LQFP100, 100-pin low-profile quad flat package outline(1)
0.25 mm 0.10 inch GAGE PLANE k D D1 D3
75 76 51
75
51
L L1 C
76
0.5
50
0.3
50
16.7
14.3
b E3 E1 E
100
26 1.2
1
100 26 25
25 12.3
Pin 1 1 identification e
ccc
C
16.7
A1
ai14906
A2 A SEATING PLANE C
1L_ME
1. Drawing is not to scale. 2. Dimensions are in millimeters.
Table 47.
Symbol
LQPF100 - 100-pin low-profile quad flat package mechanical data
millimeters Typ Min Max 1.6 0.05 1.4 0.22 1.35 0.17 0.09 16 14 12 16 14 12 0.5 0.6 1 3.5 0.0 0.08 7.0 0.45 0.75 15.8 13.8 16.2 14.2 15.8 13.8 0.15 1.45 0.27 0.2 16.2 14.2 0.6299 0.5512 0.4724 0.6299 0.5512 0.4724 0.0197 0.0236 0.0394 3.5 0.0 0.0031 7.0 0.0177 0.0295 0.622 0.5433 0.6378 0.5591 0.0551 0.0087 0.002 0.0531 0.0067 0.0035 0.622 0.5433 Typ inches(1) Min Max 0.063 0.0059 0.0571 0.0106 0.0079 0.6378 0.5591
A A1 A2 b c D D1 D3 E E1 E3 e L L1 k ccc
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
STM32F101xx Figure 36. Recommended footprint(1)(2)
Figure 35. LQFP64 - 64 pin low-profile quad flat package outline(1)
D D1 A1 A A2
48
33 0.3
49
0.5
32
b
12.7
10.3
E1
E e
10.3 64 17 1.2 1
c
16 7.8 12.7
L1 L
ai14398
ai14909
1. Drawing is not to scale. 2. Dimensions are in millimeters.
Table 48.
Dim.
LQFP64 - 64-pin low-profile quad flat package mechanical data
mm Min Typ Max 1.60 0.05 1.35 0.17 0.09 12.00 10.00 12.00 10.00 0.50 0 0.45 3.5 0.60 1.00 Number of pins 7 0.75 0 0.0177 1.40 0.22 0.15 1.45 0.27 0.20 0.0020 0.0531 0.0067 0.0035 0.4724 0.3937 0.4724 0.3937 0.0197 3.5 0.0236 0.0394 7 0.0295 0.0551 0.0087 Min inches(1) Typ Max 0.0630 0.0059 0.0571 0.0106 0.0079
A A1 A2 b c D D1 E E1 e L L1
N
64
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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STM32F101xx
Package characteristics
Figure 37. LQFP48 - 48-pin low-profile quad flat package outline(1)
D D1 A1 b A A2
Figure 38. Recommended footprint(1)(2)
0.50 1.20
13 12
24 25
0.30
9.70
5.80
7.30
0.20
E1
E
e
1 48
7.30 36 37
1.20
L1 L
ai14384
c
5.80 9.70
ai14911
1. Drawing is not to scale. 2. Dimensions are in millimeters.
Table 49.
Dim.
LQFP48 - 48-pin low-profile quad flat package mechanical data
mm Min Typ Max 1.60 0.05 1.35 0.17 0.09 9.00 7.00 9.00 7.00 0.50 0 0.45 3.5 0.60 1.00 Number of pins 7 0.75 0 0.0177 1.40 0.22 0.15 1.45 0.27 0.20 0.0020 0.0531 0.0067 0.0035 0.3543 0.2756 0.3543 0.2756 0.0197 3.5 0.0236 0.0394 7 0.0295 0.0551 0.0087 Min inches(1) Typ Max 0.0630 0.0059 0.0571 0.0106 0.0079
A A1 A2 b C D D1 E E1 e L L1
N
48
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
STM32F101xx
6.2
Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in Table 7: General operating conditions on page 28. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where:

TA max is the maximum ambient temperature in C, JA is the package junction-to-ambient thermal resistance, in C/W, PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH),
PI/O max represents the maximum power dissipation on output pins where: taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 50.
Symbol
Thermal characteristics
Parameter Thermal resistance junction-ambient LQFP 100 - 14 x 14 mm / 0.5 mm pitch Thermal resistance junction-ambient LQFP 64 - 10 x 10 mm / 0.5 mm pitch Thermal resistance junction-ambient LQFP 48 - 7 x 7 mm / 0.5 mm pitch Thermal resistance junction-ambient VFQFPN 36 - 6 x 6 mm / 0.5 mm pitch Value 46 45 C/W 55 18 Unit
JA
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org.
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STM32F101xx
Ordering information scheme
7
Ordering information scheme
Table 51.
Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 101 = access line Pin count T = 36 pins C = 48 pins R = 64 pins V = 100 pins Flash memory size 6 = 32 Kbytes of Flash memory 8 = 64 Kbytes of Flash memory B = 128 Kbytes of Flash memory Package H = BGA T = LQFP U = VFQFPN Temperature range 6 = Industrial temperature range, -40 to 85 C. Options xxx = programmed parts TR = tape and real
Ordering information scheme
STM32 F 101 C 6 T 6 xxx
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office.
7.1
Future family enhancements
Further developments of the STM32F101xx access line will see an expansion of the current options. Larger packages will soon be available with up to 512 KB Flash, 48 KB SRAM and with extended features such as flexible static memory controller (FSMC) support, DAC and additional timers and USARTS.
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Revision history
STM32F101xx
8
Revision history
Table 52.
Date 06-Jun-2007
Document revision history
Revision 1 First draft. IDD values modified in Table 11: Maximum current consumption in Run and Sleep modes (TA = 85 C). VBAT range modified in Power supply schemes. VREF+ min value, tSTAB, tlat and fTRIG added to Table 41: ADC characteristics. Table 37: TIMx characteristics modified. Note 6 modified and Note 8, Note 4 and Note 7 added below Table 3: Pin definitions. Figure 18: Low-speed external clock source AC timing diagram, Figure 10: Power supply scheme, Figure 22: Recommended NRST pin protection and Figure 23: I2C bus AC waveforms and measurement circuit(1) modified. Sample size modified and machine model removed in Electrostatic discharge (ESD). Number of parts modified and standard reference updated in Static latchup. 25 C and 85 C conditions removed and class name modified in Table 32: Electrical sensitivities. tSU(LSE) changed to tSU(LSE) in Table 21: HSE 4-16 MHz oscillator characteristics. In Table 28: Flash memory endurance and data retention, typical endurance added, data retention for TA = 25 C removed and data retention for TA = 85 C added. Note removed below Table 7: General operating conditions. VBG changed to VREFINT in Table 10: Embedded internal reference voltage. IDD max values added to Table 11: Maximum current consumption in Run and Sleep modes (TA = 85 C). IDD(HSI) max value added to Table 23: HSI oscillator characteristics. RPU and RPD min and max values added to Table 33: I/O static characteristics. RPU min and max values added to Table 36: NRST pin characteristics (two notes removed). Datasheet title corrected. USB characteristics section removed. Features on page 1 list optimized. Small text changes. Changes
20-Jul-07
2
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STM32F101xx Table 52.
Date
Revision history Document revision history (continued)
Revision Changes VESD(CDM) value added to Table 31: ESD absolute maximum ratings. Note added below Table 9: Embedded reset and power control block characteristics. and below Table 21: HSE 4-16 MHz oscillator characteristics. Note added below Table 34: Output voltage characteristics and VOH parameter description modified. Table 41: ADC characteristics and Table 43: ADC accuracy - limited test conditions modified. Figure 27: ADC accuracy characteristics modified. Packages are ECOPACK(R) compliant. Tables modified in Section 5.3.5: Supply current characteristics. ADC and ANTI_TAMPER signal names modified (see Table 3: Pin definitions). Table 3: Pin definitions modified. Note 4 removed and values updated in Table 17: Typical current consumption in Standby mode. Vhys modified in Table 33: I/O static characteristics. Updated: Table 29: EMS characteristics and Table 30: EMI characteristics. tVDD modified in Table 8: Operating conditions at power-up / power-down. Typical values modified, note 2 modified and note 3 removed in Table 25: Low-power mode wakeup timings. Maximum current consumption Table 11, Table 12 and Table 13 updated. Values added and notes added in Table 14: Typical and maximum current consumptions in Stop and Standby modes. On-chip peripheral current consumption on page 38 added. Package mechanical data inch values are calculated from mm and rounded to 4 decimal digits (see Section 6: Package characteristics). Vprog added to Table 27: Flash memory characteristics. TS_temp added to Table 45: TS characteristics. TS_vrefint added to Table 10: Embedded internal reference voltage. Handling of unused pins specified in General input/output characteristics on page 48. All I/Os are CMOS and TTL compliant. Table 3: Pin definitions: table clarified and Note 7 modified. Internal LSI RC frequency changed from 32 to 40 kHz (see Table 24: LSI oscillator characteristics). Values added to Table 25: Low-power mode wakeup timings. NEND modified in Table 28: Flash memory endurance and data retention. Option byte addresses corrected in Figure 7: Memory map. ACCHSI modified in Table 23: HSI oscillator characteristics. tJITTER removed from Table 26: PLL characteristics. Appendix A: Important notes on page 71 added. Added: Figure 12, Figure 13, Figure 14 and Figure 16.
18-Oct-2007
3
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Revision history Table 52.
Date
STM32F101xx Document revision history (continued)
Revision Changes Document status promoted from preliminary data to datasheet. Small text changes. STM32F101CB part number corrected in Table 1: Device summary. Number of communication peripherals corrected for STM32F101Tx in Table 2: Device features and peripheral counts (STM32F101xx access line) and Number of GPIOs corrected for LQFP package. Power supply schemes on page 10 modified. Main function and default alternate function modified for PC14 and PC15 in Table 3: Pin definitions, Note 5 added, Remap column added. Figure 10: Power supply scheme modified. VDD -VSS ratings modified and Note 1 modified in Table 4: Voltage characteristics. Note 1 modified in Table 5: Current characteristics. Note 2 added in Table 9: Embedded reset and power control block characteristics. 48 and 72 MHz frequencies removed from Table 11, Table 12 and Table 13. MCU `s operating conditions modified in Typical current consumption on page 35. IDD_VBAT typical value at 2.4 V modified and IDD_VBAT maximum value added in Table 14: Typical and maximum current consumptions in Stop and Standby modes. Note added in Table 15 on page 35 and Table 16 on page 36. Table 18: Peripheral current consumption modified. Figure 15: Current consumption in Stop mode with regulator in Lowpower mode versus temperature at VDD = 3.3 V and 3.6 V added. Note removed below Figure 24: SPI timing diagram - slave mode and CPHA=0. Note added below Figure 25: SPI timing diagram - slave mode and CPHA=1(1). Figure 28: Typical connection diagram using the ADC modified. tSU(HSE) and tSU(LSE) conditions modified in Table 21 and Table 22, respectively. Maximum values removed from Table 25: Low-power mode wakeup timings. tRET conditions modified in Table 28: Flash memory endurance and data retention. Conditions modified in Table 29: EMS characteristics. Impedance size specified in A.4: Voltage glitch on ADC input 0 on page 71. Small text changes in Table 34: Output voltage characteristics. Section 5.3.11: Absolute maximum ratings (electrical sensitivity) updated. Details on unused pins removed from General input/output characteristics on page 48. Table 40: SPI characteristics updated. Notes added and Ilkg removed in Table 41: ADC characteristics. Note added in Table 42 and Table 45. Note 2 and Note 3 added below Table 43: ADC accuracy - limited test conditions. Avg_Slope and V25 modified in Table 45: TS characteristics. JAvalue for VFQFPN36 package added in Table 50: Thermal characteristics. I2C interface characteristics on page 52 modified. Order codes replaced by Section 7: Ordering information scheme.
22-Nov-2007
4
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STM32F101xx Table 52.
Date
Revision history Document revision history (continued)
Revision Changes Figure 2: Clock tree on page 15 added. CRC added (see CRC (cyclic redundancy check) calculation unit on page 9 and Figure 7: Memory map on page 23 for address). Maximum TJ value given in Table 6: Thermal characteristics on page 28. PD, TA and TJ added, tprog values modified and tprog description clarified in Table 27: Flash memory characteristics on page 45. IDD modified in Table 14: Typical and maximum current consumptions in Stop and Standby modes on page 33. ACCHSI modified in Table 23: HSI oscillator characteristics on page 43, note 2 removed. tRET modified in Table 28: Flash memory endurance and data retention. VNF(NRST) unit corrected in Table 36: NRST pin characteristics on page 51. Table 40: SPI characteristics on page 55 modified. IVREF added in Table 41: ADC characteristics on page 58. Table 43: ADC accuracy - limited test conditions added. Table 44: ADC accuracy modified. LQFP100 package specifications updated (see Section 6: Package characteristics on page 63). Recommended LQFP100, LQFP64, LQFP48 and VFQFPN36 footprints added (see Figure 34, Figure 36, Figure 38 and Figure 32). Section 6.2: Thermal characteristics on page 68 modified. Appendix A: Important notes removed. Small text changes. In Table 28: Flash memory endurance and data retention: - NEND tested over the whole temperature range - cycling conditions specified for tRET - tRET min modified at TA = 55 C Figure 2: Clock tree corrected. Figure 7: Memory map clarified. V25, Avg_Slope and TL modified in Table 45: TS characteristics. CRC feature removed.
14-Mar-2008
5
21-Mar-2008
6
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STM32F101xx
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